{"slug":"hdldiagzero","title":"hdldiagzero","description":"Generate clean SVG block diagrams of HDL/RTL/SoC designs. Color-codes by clock domain, distinguishes AXI-MM/Lite/Stream, draws CDC blocks with split fill, omits clock/reset/JTAG/debug clutter, and validates output geometry.","developer":null,"category":"development","reported_installs":null,"active":true,"first_seen_at":"2026-10-03T22:13:33.942Z","last_seen_at":"2026-10-10T06:02:50.945Z","last_changed_at":"2026-10-03T22:13:33.942Z","platform":"claude","sources":["Community"],"works_with":["Claude Code"],"marketplace_url":null,"repository_url":"https://github.com/lcapossio/hdldiagZero.git","web_data":{},"github_data":{},"catalog_sources":{"community":[{"name":"hdldiagzero","source":{"sha":"a96e4cc5cb91f6dc510b9fb6d2fc064821ed249d","url":"https://github.com/lcapossio/hdldiagZero.git","source":"url"},"category":"development","homepage":"https://github.com/lcapossio/hdldiagZero","description":"Generate clean SVG block diagrams of HDL/RTL/SoC designs. Color-codes by clock domain, distinguishes AXI-MM/Lite/Stream, draws CDC blocks with split fill, omits clock/reset/JTAG/debug clutter, and validates output geometry."}]}}